(a) Field of the Invention
The present invention relates to a system-on-chip development apparatus for wire/wireless Internet phone. More specifically, the present invention relates to a system-on-chip development apparatus that is indispensable to the development of wire/wireless Internet telephones that provide free or inexpensive voice telephone and Internet access functions on the worldwide Internet network.
(b) Description of the Related Art
Conventionally, a separate RISC (Reduced Instruction Set Computer) core to provide an internal processor function, an FPGA (Field Programmable Gate Array) to use the RISC core, and additional PDGAs to develop peripheral devices have been necessarily used in the development of system-on-chips. In addition, a system-on-chip development apparatus for wire/wireless Internet telephone must be independently constructed and limitedly used. Hence, the circuit configuration becomes more complex with a large number of complicated connection lines between the RISC core and the FPGAs which makes signals unstable, and the scale of the system increases with unnecessary functions.
In using an ARM920T RISC core, for example, there are necessarily used one FPGA to use the RISC core in addition to the RISC and a plurality of FPGAs to develop at least one peripheral device. The bus clock frequency for connecting the FPGAs and the RISC core is confined to about 20 to 40 MHz according to the FPGA characteristic. The use of a separate RISC core and FPGAs makes it impossible to perform testing of the RISC core using the maximum clock frequency of the RISC core. This results in difficulty of designing and developing the system-on-chip development apparatus and requires too much time in debugging and development.